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ISO1I811T
Functional Description
3.8
Serial Interface Mode
The ISO1I811T contains a serial interface that can be activated by pulling the SEL pin to logic High state. It can
be directly controlled by the microcontroller output ports. The output pin SDO is in state “Z” as long as CS=1.
Otherwise, the bits are sampled with the falling edge of CS. Subsequently with every falling edge of SCLK the bits
are provided serially to the pin SDO. At the same time, the input to SDI is put into an 8bit FIFO buffer sampled with
the rising edge of SCLK. When all 8 internally sampled bits have been put to SDO, the buffered bits from the input
SDI are provided to the serial output pin SDO (Daisy Chain Mode).
The timing requirements for the parallel interface are shown in Figure 11 and in Table 15 .
/CS
inactive
t SCLK_su
active
t CSD
t SCLK
SCLK
t SU
receive
edge
t HD
transmit
edge
t SU t CSH
SDI
MSB
LSB
t CS_valid
t SCLK_valid
t float
SDO
Figure 11
Serial Bus Timing
MSB
LSB
Several SPI topologies are supported: pure bus topology and daisy-chain ( Figure 12 ). Of course independent
individual control with dedicated SPI controller interfaces for each slave IC are possible, as well.
A
SCLK
SDO
SCLK
MISO
A
SCLK
SDO
SCLK
MISO
SDI
/CS
/CS
B
SCLK
SDO
B
SCLK
SDO
SDI
/CS
MCU
or
/CS
MCU
or
C
SCLK
ASIC
C
SCLK
ASIC
SDO
/CS
SDO
SDI
/CS
D
SCLK
SDO
D
SCLK
SDO
SDI
/CS
/CS
spi_topologies .vsd
Figure 12
Example SPI Topologies
Data Sheet
16
Revision 2.0, 2012-06-14
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